1. Field of the Invention
The present invention relates to stress testing integrated circuits. More particularly, this invention relates to stress testing integrated circuits in which serial data is communicated by altering the duty cycle of a signal within that integrated circuit.
2. Description of the Prior Art
It is known to perform tests on integrated circuits comprising serial receivers which receive serialized data from serial transmitters over high speed serial links. Such testing, for example shortly after manufacturing, involves artificially downgrading the quality of the signal sent over the serial link in order to test how well the serial receiver copes with that poor quality data and whether it can still recover the original data that was transmitted. A receiver's ability to cope with such distorted signals is referred to as its jitter tolerance.
Typically, a external programmable signal generator is used to provide the source of the variation in the serial data. The distorted signal used for testing jitter tolerance is commonly referred to as a stressed eye. Such a stressed eye may comprise variation in the duty cycle of a transmitted signal. Currently, the primary method for testing jitter tolerance is to create a stressed eye off-chip using high speed test equipment. Such equipment may, for example, create a serial data stream to be received by a serial receiver in which the duty cycle is distorted.
Such high speed test equipment is expensive and complex and hence it is desirable to provide an improved technique for testing integrated circuits.